Method for precisely controlled masked anodization

ABSTRACT

The present invention is related to a method for masked anodization of an anodizable layer on a substrate, for example an aluminum layer present on a sacrificial layer, wherein the sacrificial layer needs to be removed from a cavity comprising a Micro or Nano Electromechanical System (MEMS or NEMS). Anodization of an Al layer leads to the formation of elongate pores, through which the sacrificial layer can be removed. According to the method of the invention, the anodization of the Al layer is done with the help of a first mask which defines the area to be anodized, and a second mask which defines a second area to be anodized, said second area surrounding the first area. Anodization of the areas defined by the first and second mask leads to the formation of an anodized structure in the form of a closed ring around the first area, which forms a barrier against unwanted lateral anodization in the first area.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. §119(e) of U.S.Provisional Application No. 61/418,194, filed Nov. 30, 2010, thedisclosure of which is hereby expressly incorporated by reference in itsentirety and is hereby expressly made a portion of this application.

FIELD OF THE INVENTION

Methods for precisely controlling a masked anodization process areprovided. The preferred embodiments are further related to manufacturingsemiconductor devices, especially to methods of encapsulation and tosuch devices. More specifically they may relate to zero-Level or waferlevel packaging of semiconductor devices. More particularly, thepreferred embodiments relate to Nano- and/or Micro-Electro-MechanicalSystems (NEMS and/or MEMS) and to processes of encapsulating (orpackaging) said systems.

BACKGROUND OF THE INVENTION

Creating patterns of a dielectric or porous material within a conductivethin film by means of masked anodization (wet electrochemical oxidationand/or etching) has several advantages over conventional thin filmdeposition and etching techniques, such as the simplicity of thefabrication process and the relatively planar (and aligned) structuresthat result from such process. Masking the anodization process isnormally achieved by applying a masking structure on top of the layer tobe anodized. The masking structure can be applied by means ofconventional photolithography (photoresist mask) or by means ofdeposition and patterning of another material that is resistant to theanodization process (hard mask). A photoresist mask is simpler toimplement than a hard mask but photoresists are normally attacked duringthe anodization process resulting in poor control over the lateralextent of the anodized patterns.

Finding a simple technique for high-precision masked anodization isnecessary to fabricate planar patterns of a dielectric or porousmaterial within a conductive thin film. Such patterns are for exampleuseful to create interconnecting metal lines (patterns) which areisolated from each other by a porous dielectric material of lowdielectric constant which provides the advantage of reduced capacitancebetween the interconnecting lines. Because of this, the speed of signalsthat can be transmitted through these interconnects can be increased andthe cross-coupling between the different interconnects can be reduced,resulting in better performance for integrated circuits.

Another application requiring a high-precision masked anodization is thepackaging (encapsulation) of Nano- and/or Micro-Electro-MechanicalSystems (NEMS/MEMS). Said NEMS/MEMS systems cannot be directly packagedin a plastic or ceramic package, the so-called first level package,since NEMS/MEMS are often composed of fragile and/or mobilefree-standing parts that can easily be damaged during dicing andassembly. To avoid such damage, NEMS/MEMS devices have to be protectedat the wafer level, before dicing. This is possible by the so-calledzero-level packaging or wafer-level packaging techniques. Most NEMS/MEMSsystems therefore require an encapsulation under vacuum or under acontrolled atmosphere and pressure in order to ensure either a goodperformance or an acceptable lifetime of operation. The encapsulationhas to be performed without the direct deposition of sealing material onthe NEMS/MEMS device, as such deposition can cause damage to the device.Therefore there is a need to deposit first an encapsulation made of alayer having holes (pores) through which a vacuum and/or controlledatmosphere can be realized and thereafter deposit a sealing layer. Asimple and cheap process led to the idea of encapsulating NEMS/MEMSdevices with a porous membrane. This facilitates the manufacturing ofthe device as it avoids the need to shape access holes in the membraneusing photolithography since the device can be released through thepores of the membrane.

Porous alumina (AlOx) membranes are recently being investigated for useas porous membranes in said thin film vacuum packaging of NEMS/MEMSdevices as shown in FIG. 1, which shows a schematic image of a substrate1 (e.g. Si), carrying on its surface a MEMS device 2, encapsulated by aporous membrane 3. The membrane 3 is covered by a sealing layer 4. Theporous membrane 3 is obtained by anodization of an aluminum thin film(deposited on top of a dielectric thin film) in a low-pH electrolyte,and using a patterned photoresist layer as the mask. The anodizationprocess may be performed on masked Al layers using a photoresist mask(Hellin Rico et al., J. Electrochem. Soc. Vol. 154, No. 9 (2007)). Thepores 5 (not drawn to scale), are elongate openings through themembrane's thickness, through which pores the release of the MEMS device2 takes place, which is the etching away of a sacrificial layerdeposited onto the MEMS device prior to the deposition of the membranelayer 3. This masked anodization process using photoresist has thedrawback that the openings in the photoresist do not appropriately limitthe anodization process to the desired area, as shown in FIG. 2. Thisfigure shows the substrate 1, with a dielectric thin film 11 on thesurface of the substrate, and a membrane layer 12 on the thin film 11. Aphotoresist mask 13 covers the membrane film except for a portion 14which defines the area of the membrane which is to be anodized. Asdescribed in more detail further, anodization generally takes place bysubmerging the substrate into an anodization bath. When the substrate isleft too long in the anodization bath, anodization continues until ananodized region 15 is formed which is too wide (see borders 16), i.e.unwanted continuous growth of the anodized region occurs.

Especially when applying the anodization voltage to a full wafer orlarge area substrate comprising the layer to be anodized and leaving thesubstrate (wafer) in the anodization bath results in said unwantedcontinuous growth of the anodized region beyond the limits defined bythe photoresist mask. The problem of performing the masked anodizationprocess on a full wafer scale is the fact that areas defined by themasks being present in the central areas (middle) of the substrate(wafer) surface are not yet completely anodized while the areas definedby the masks being present around the substrate (wafer) edges arealready completely anodized and will become over-anodized. The problemof unwanted continuous growth is caused by edge peeling (resulting in“undercut”) of the photoresist mask due to:

-   -   (1) Attack by the high-acidity level electrolyte,    -   (2) Expansion of the AlOx thin film, and    -   (3) Gas formations occurring during the anodization process.

Hence there still exists a problem in state of the art techniques toprovide a reliable and controllable method for providingprecisely-defined anodized patterns within a conductive layer using aphotoresist mask, and the application of such anodized patterns toprovide for example a thin film vacuum packaging for NEMS/MEMS.

SUMMARY OF THE INVENTION

It is an object to provide an improved method for creating precisepatterns of anodized material within an anodizable layer by means ofmasked anodization. More specifically it is an object to create precisepatterns of a dielectric or porous material within a conductive thinfilm using masked anodization. It is thereby in particular an object toprovide an improved and cost-efficient masked anodization process forapplication in manufacturing of semiconductor devices on (full) waferscale to make the anodization process applicable in large scaleproduction of semiconductor devices.

It is further an object of preferred embodiments to provide a reliableand controllable method for performing wet anodization processes whichlocally transform an anodizable layer e.g. a conductive (metal) layerinto an anodized layer e.g. a dielectric or porous layer. It is the goalof the preferred embodiments to perform said anodization uniformly on a(full) wafer scale.

A further object is to provide a micro-electronic process technology forNano- and Micro Electro Mechanical Systems (NEMS/MEMS) in order toachieve a controllable and uniform (full) wafer scale encapsulation orpackaging process for said NEMS/MEMS devices.

The above objectives are accomplished by a method and device accordingto the preferred embodiments. The preferred embodiments solve theproblem of achieving a uniform and controllable anodization bysurrounding a group (plurality) of mask structures with an additionalsurrounding mask structure. In other words the problem is solved byusing an additional surrounding photoresist or other mask structure withhigh precision which defines small areas on the surface to be exposedselectively to the anodization process without causing over-anodizationleading towards delamination or undercut of the mask layer during theanodization. The presence of said additional surrounding mask structureresults in self-limitation of the anodization process as the anodizedborder becomes anodized (oxidized) simultaneously with the anodizedareas within said border, so that said border prevents furtheranodization current from reaching the anodized region of the maskstructures to avoid unwanted further anodization. Since the electricalcurrent needed for the anodization process is supplied at the edge(perimeter) of the substrate, surrounding every group of structures onthe anodization mask with an additional surrounding mask structure(defining a borderline of anodized material) results in self-limitationof the anodization process as the anodized border becomes simultaneouslyanodized (oxidized) and prevents further anodization current fromreaching the anodized region. The additional surrounding mask structure(defining the borderline or protection ring) may be applied at differentscales during the mask design for the anodization process (i.e. theborderline can surround a small group or a large group of structures, orpossibly surround the whole substrate (wafer). The width of theadditional surrounding mask structure and the surrounded area can bechosen (or adjusted) to guarantee a full vertical anodization of theenclosed structures, and at the same time protect these structures fromlarge lateral extensions of the anodization process.

By applying the masked anodization process according to the preferredembodiments in a packaging process for NEMS/MEMS devices, an additionalsurrounding mask structure is surrounding a group of individualNEMS/MEMS devices and will result in self-limitation of the anodizationprocess as the anodized border becomes simultaneously anodized(oxidized) and prevents further anodization current from reaching theanodized region of the mask structures to avoid unwanted furtheranodization.

It is an advantage of preferred embodiments that providing theadditional surrounding mask structure does not need extra processingsteps as said additional mask structure may be provided simultaneouslywith the provision of the first mask structure(s).

The preferred embodiments are thus related to a method as disclosed inthe appended claims. Particular and preferred aspects are set out in theaccompanying independent and dependent claims. Features from thedependent claims may be combined with features of the independent claimsand with features of other dependent claims as appropriate and notmerely as explicitly set out in the claims.

As such, the preferred embodiments are related to a method for maskedanodization, said method comprising the steps of

-   -   providing a substrate,    -   providing an anodizable layer on said substrate,    -   providing on said anodizable layer at least one first mask        defining one or more first structures to be anodized and an        additional second mask defining a second structure to be        anodized, said second structure surrounding said one or more        first structures,    -   anodizing said anodizable layer in the regions defined by the        first and second mask in order to create anodized structures,    -   removing the first and second mask.        The expression ‘anodizing said anodizable layer in the regions        defined by the first and second mask’ means that the anodization        continues until the layer is anodized over the totality of its        thickness in said regions. With ‘surrounding’ is meant that the        second structure forms a closed ring structure around the first        structure(s).

According to the preferred embodiment, the step of anodizing saidanodizable layer is performed by inserting the substrate in anelectrolyte and applying a voltage (or electrical current) on saidsubstrate.

The step of anodizing said anodizable layer may also be performed usinga two-step anodization process comprising a first anodizing step to forma first anodized layer, followed by a second anodizing step afteretching away the first anodized layer.

According to a preferred embodiment, the step(s) of anodizing is(are)performed by inserting the substrate in an electrolyte selected from thegroup consisting of sulfuric acid, phosphoric acid, oxalic acid,hydrofluoric acid, ethanol, isopropyl alcohol, and mixtures of thesechemicals.

According to the preferred embodiment, said anodizing step(s) produce(s)elongate pores in said anodized structure(s), said pores extending fromthe front surface to the back surface of said anodizable layer.

According to an embodiment, the anodizable layer is an Al layer and thestep(s) of anodizing is(are) performed by inserting the substrate in asulfuric acid based electrolyte at temperatures in the range of 20-40°C. and applying a voltage of around 20V.

According to an embodiment, the anodizable layer is a metal layer whichis to be anodized to form a metal oxide layer, and said anodization bathcomprises an etchant suitable for etching said oxide, and wherein saidanodization step comprises a first time period during which said voltageis applied, said voltage being removed at the end of said first timeinterval, and a second time period following said first time period,during which second period the substrate is left in said bath, tothereby remove a barrier layer at the bottom of said pores. In thelatter embodiment, said metal may be aluminum and said etchantphosphoric acid.

According to an embodiment:

-   -   said step of providing a substrate comprises depositing a        sacrificial layer onto a base substrate, said anodizable layer        is provided onto said sacrificial layer,    -   said first mask defines a structure to be a anodized,    -   said anodizing step(s) produce(s) elongate pores in said        anodized structure, said pores extending from the front surface        to the back surface of said anodizable layer,    -   at least a portion of the sacrificial layer is removed through        said pores, so as to form a cavity, and    -   a sealing layer is applied onto said anodized structures in        order to seal off said cavity.

In the latter embodiment, the sacrificial layer can be made of amaterial selected from the group consisting of polycrystalline SiGe,oxide-based or nitride-based films, polymer, single crystal orpolycrystalline Si. In the latter embodiment, said substrate maycomprise a NEMS/MEMS device, which is(are) encapsulated in said cavity.

In the latter case, the step of removing at least some of thesacrificial material is performed using a selective wet or dry etchingthat does not damage the enclosed NEMS/MEMS device.

In the latter embodiment, the sacrificial layer may be silicon-oxide andthe selective etching may be performed using a vapor-phase hydrofluoric(HF) acid mixed with other gases such as nitrogen and ethanol or watervapor in a reduced-pressure chamber.

In the latter embodiment, the sacrificial layer may be a polymer-basedmaterial and the selective etching may be performed using a dry plasmaetching in a low-pressure chamber in the presence of oxygen ions.

In the latter embodiment, the sealing layer may be:

-   -   a conductive layer such as Al, Cu, Ni, polycrystalline Si or        SiGe, or    -   a dielectric material such as oxide- or nitride-based silicon        compounds, or    -   a polymer, or    -   a combination or a stack of two or more materials,        Said sealing layer may be deposited using an evaporation        technique or a chemical (CVD) or physical vapor deposition (PVD)        technique in a low-pressure chamber.

In the method of the preferred embodiments, the anodizable layer may bea metal layer or semiconducting layer. Said anodizable layer may beselected from the group consisting of Al, Ta, Ti, Cu, Ni,polycrystalline Si, polycrystalline SiGe.

In the method of the preferred embodiments, the mask structures may beformed by photolithographic patterning of a photosensitive layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates the concept of thin film MEMS packaging using aporous membrane as known in the prior art.

FIG. 2 illustrates the large lateral extension of the Al anodizationprocess using a photoresist mask (problem to be solved by the preferredembodiments).

FIG. 3 a illustrates an intermediate stage during the anodizationprocess whereby the anodization current may still reach the anodizationregion before the vertical anodization is complete.

FIG. 3 b is a top view of a wafer comprising several masks and providedwith a ring electrode arranged along the circumference of the wafer.

FIG. 3 c illustrates the final stage of the anodization process (whenthe vertical anodization is complete) whereby the borderline iscompletely anodized (oxidized) forming a dielectric isolation ringaround the anodization region which blocks further supply of theelectric charges needed for anodization.

FIGS. 4 a-4 d illustrate different steps in a suitable process flow touse the masked anodization process for thin film packaging of aNEMS/MEMS device according to preferred embodiments.

FIG. 4 a illustrates the step of depositing a metal layer on top of thesacrificial layer covering the NEMS/MEMS structure and interconnects.

FIG. 4 b illustrates the step of masked anodization and thin barrieroxide layer removal.

FIG. 4 c illustrates the step of removing the sacrificial layer anddepositing a sealing layer.

FIG. 4 d illustrates the step of removing the layers covering the metalpads for electrical access and illustrates the final NEMS/MEMS deviceencapsulation.

FIGS. 5 a and 5 b illustrate the form the pores formed by anodization ofan Aluminum layer, and the oxide barrier layer formed at the bottom ofthe pores.

FIG. 6 illustrates an example of a mask design defining a ring structurein accordance with the preferred embodiments.

The drawings are only schematic and are non-limiting. In the drawings,the size of some of the elements may be exaggerated and not drawn onscale for illustrative purposes. Any reference signs in the claims shallnot be construed as limiting the scope. In the different drawings, thesame reference signs refer to the same or analogous elements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

According to an aspect of the preferred embodiments, a method isprovided for uniform and controllable masked anodization, said methodcomprising at least the steps of (with reference to FIG. 3):

-   -   providing (i.e. supplying or producing) a substrate (10,11), and        then    -   providing an anodizable layer (12) on said substrate, and then    -   providing on said anodizable layer (12) at least one first mask        (20) defining the dimensions of one or more first structures        (21) to be anodized and an additional second mask (22) defining        a second structure (23) to be anodized, said second structure        surrounding said first structure(s), and then    -   anodizing said anodizable layer (12) in the regions defined by        the first (20) and second (22) mask in order to create anodized        structures (21,23), and then    -   removing the mask structures (20,22).

FIG. 3 a shows again a substrate 10. In this embodiment (but notlimiting to the scope of the preferred embodiments), a dielectric layer11 is deposited on the substrate, which may for example be a sacrificiallayer. Layer 12 is a membrane layer and layer 13 is a mask layer,preferably a patterned photoresist layer. The mask layer comprises atleast one first mask 20, which defines the areas 21 which are to beanodized. The mask layer further comprises a second mask 22 whichdefines an area 23 which surrounds said one or more first areas 21 to beanodized, forming a closed ring structure (not necessarily acircular-shaped ring) around said areas 21. FIG. 3 b shows a top view ofa semiconductor wafer 30 carrying on its surface the mask layer 13 whichcomprises a plurality of masks 20 which define areas 21 to be anodized.Around each mask 20 (and thus around each group of areas 21), the masklayer defines a ring structure 23 to be anodized which encircles themasks 20. The ‘second mask structure’ 22 thus corresponds to thetotality of the mask layer 13 minus the mask structures 20.

Along the edge of the wafer 30, an electrode 31 is placed, which is inelectrical contact with the layer 12 to be anodized (preferably a metallayer, see further). The electrode 31 will play the role of the anodeduring the anodization. This assembly is submerged in an anodizationbath, filled with an electrolyte. The second electrode (the cathode) ispart of the anodization bath (preferably a metal plate immersed in theanodization bath, facing the front side of the wafer, i.e. the sidecarrying the masks 20/22). When anodization starts, the charge flows inthe direction shown by the arrows 32 in FIGS. 3 a and 3 b, i.e. startingfrom the outer edge of the wafer 30, and from the outer edge of eachmask 20 towards the centre.

The drawing in FIG. 3 a illustrates an intermediate stage during theanodization process whereby the anodization current (charge flow) maystill reach the anodization regions 21 before the vertical anodizationis complete. FIG. 3 c illustrates the final stage of the anodizationprocess (when the vertical anodization is complete) whereby the ringstructure 23 is completely anodized (oxidized), thereby acting asborderline and hence forming a dielectric isolation ring around theanodization regions 21, which blocks further supply of the electriccharges needed for anodization.

According to embodiments, the material for use as anodizable layer 12may be a metal or semiconducting layer which is selected from Al, Ta,Ti, Cu, Ni, polycrystalline Si, polycrystalline SiGe, etc. For exampleAluminum layers may be used of around 0.5-10 μm thick which may bedeposited e.g. by using a sputtering process performed at lowtemperature. Prior to anodizing, the Al layers may be cleaned by placingthem in an ultrasonic bath of deionized water.

According to embodiments, the first and second mask structures 20,22 maybe formed by state of the art photolithographic patterning of aphotosensitive layer (resist). The advantage of using a photoresist(photosensitive layer) is the simplicity of forming the mask structurescompared to other techniques involving deposition and patterning (bychemical or physical etching) of another mask material.

According to embodiments, the step of anodizing said anodizable layer 12may lead to the formation of a porous (metal) layer. The pores (holes)in said porous layer may have a length greater than ten times theirwidth, and a width in the range 5-200 nm, e.g. 20 nm or between 20 nmand 200 nm, or between 5 and 20 nm.

According to embodiments, the step of anodizing said anodizable (metal)layer 12 may be performed by means of a one-step anodization process. Asalready mentioned, said one step-anodization process may be performed byinserting the substrate in an electrolyte and applying a voltage (orelectrical current) on said substrate. Said electrolyte may be sulfuricacid, phosphoric acid, oxalic acid, hydrofluoric acid, ethanol,isopropyl alcohol, or a mixture of these or other chemicals. By applyinga voltage in the range of 5-200V, pores are formed on the surface of theanodizable (metal) layer which are distributed randomly or in ahexagonal order. To achieve better hexagonal order of the pores,optimized process conditions (anodization voltage, electrolyte, andtemperature) should be chosen to reach the best volume expansion factorfor the porous layer.

According to embodiments, the step of anodizing said anodizable (metal)layer 12 may be performed by means of a two-step anodization process.Said two step-anodization process may be performed by first applying ashort anodizing step which patterns the surface of the anodizable(metal) layer 12. Later, this patterned surface acts as self-assembledmarks for the second anodizing step (Mei et al., “Formation mechanism ofalumina nanotubes and nanowires from highly ordered porous anodicalumina template,” Journal of Applied Physics, Vol. 97, 034305 (2005)).An extended second anodizing step, after etching away the first anodizedlayer not only improves the regularity of the cell arrangement but alsoreduces the number of defects and dislocations. A third anodizing stepdoes not significantly improve the ordering of the pores and the size ofthe well-ordered domains.

According to embodiments, the voltage (current) applied to achieveanodization of the anodizable (metal) layer is applied between theanodizable (metal) layer on the substrate and the electrolyte or areference electrode therein. The voltage applied for anodizing lies inthe range between a few volts and a few hundreds of volts. A voltage of20V can be used for example when performing anodization in a sulfuricacid based electrolyte at temperatures in the range of 20-40° C.

According to embodiments, when the anodization of the additionalstructure 23 (vertical anodization) is complete, said additionalstructure forms a protective structure 23 acting as a dielectricisolation ring which blocks further supply of the electric chargesneeded for anodization and thereby avoids unwanted extension of theanodized structures 21 surrounded by the additional structure 23.

According to embodiments, the anodizable (metal) layer may be anAluminum layer and the anodization process conditions may be optimizedfor a given electrolyte, such as anodizing voltage and temperature, andacid concentration. Synthesis of porous aluminum oxide (AlO_(x))membranes can start from a sputter-deposited or evaporated Al film. Themain anodizing parameters to be selected are dependent on the type ofthe electrolyte since this affects the diameter of the pores and theinter-pore distance, voltage and temperature, and the sequence ofanodizing steps. The anodization may occur within a glass- orTeflon-based chamber in which a conductive reference electrode isinserted. The substrate 30 carrying the metal layer 12 to be anodizedmay be inserted into the anodization chamber by means of a Teflon- orpolymer-based holder which protects the edges and backside of thesubstrate from contacting the anodization electrolyte. The anodizationprocess may be performed by applying the anodization voltage (orcurrent) between the reference electrode and the anodizable (metal)layer 12 on the substrate. Once the vertical anodization is complete andthe dielectric isolation rings 23 (borderlines) are formed within theadditional mask structure 22, the anodization process is automaticallystopped because of the impossibility of electric charges to travelthrough the isolation rings 23.

According to a further aspect, a method is provided for (hermetically)sealing a cavity in a semiconductor device thereby using the uniform andcontrollable masked anodization process described in previousembodiments, said method comprising at least the steps of (withreference to FIG. 4):

-   -   providing a sacrificial layer (40) on a substrate wherein a        micro cavity is to be located in said sacrificial layer (40),        and wherein said substrate comprises a base substrate 10, a        dielectric layer 11 and a MEMS or NEMS device 50, provided with        electrical connections structures 51 to said device 50, and then    -   providing a metal membrane layer (41) having a thickness greater        than 0.5 micron on top of the sacrificial layer (40), and then    -   providing on said metal layer (41) a first mask (42) defining        the dimensions of a first structure 43 to be anodized, said        dimensions corresponding to the dimensions of the cavity and an        additional second mask defining a structure (not shown) to be        anodized surrounding said first structure (43), and then    -   anodizing said metal layer (41) to form a porous metal oxide        layer (43) having pores (holes) extending from the front surface        of said porous metal oxide layer (43) towards the back surface        of said porous metal oxide layer (43),    -   removing the mask structures and at least some of the        sacrificial layer (40) through the porous metal oxide layer        (43), to form the micro cavity (44), and    -   sealing (closing) with a sealing layer 45 the pores of said        porous layer (43) in order to form a (hermetically) sealed        cavity (44).

FIGS. 4 a-4 d illustrate different steps in a suitable process flow touse the masked anodization process for thin film packaging of aNEMS/MEMS device.

According to embodiments, the substrate (10,11,50,51) and thesacrificial layer (40) may be any substrate and layer used andcompatible with semiconductor processing, more particular NEMS/MEMSprocessing. Examples of substrates, which may be used are, for example,single crystal or polycrystalline Si, single crystal or poly-crystallineGe, glass, quartz, polymer, etc.

As shown, fragile devices 50 may be located in the cavity, said fragiledevice may be any NEMS/MEMS device requiring a vacuum or controlledatmosphere and pressure encapsulation.

According to embodiments, the sacrificial layer 40 may be made of amaterial selected from polycrystalline SiGe, oxide-based ornitride-based films, polymer, single crystal or polycrystalline Si, etc.Said sacrificial material may be a material which can be removed using awet or dry etching technique that does not extensively damage theenclosed NEMS/MEMS device (selective etching). For example a siliconoxide sacrificial layer 40 can be removed by vapor-phase hydrofluoric(HF) acid mixed with other gases (such as nitrogen and ethanol or watervapor) in a reduced-pressure chamber. Such diluted vapor-phase HFmixture can remove the sacrificial silicon oxide layer without reactingwith the NEMS/MEMS device or the porous layer surrounding the cavity.

According to embodiments, the sacrificial material 40 is filling acavity 44 which is present under said membrane layer 41. The cavity canfurther comprise a NEMS/MEMS device 50, the functioning and structure ofwhich is inert to said sacrificial material etchant. It can comprise afragile object, on which substantially no material may be depositedduring the closure process to guarantee the proper working and lifetimeof the device. In certain embodiments the cavity 44 is closed except forsaid pores and optionally a vent hole (not shown). A vent hole is anadditional hole which connects the cavity with the outside.

According to embodiments, the material for use as metal layer 41 may bea metal or semiconducting layer which is selected from Al, Ta, Ti, Cu,Ni, polycrystalline Si, polycrystalline SiGe, etc. For example Aluminumlayers of around 0.5-10 μm thick may be deposited by a sputteringprocess performed at low temperature. Prior to anodizing, the Al layersmay be cleaned by placing them in an ultrasonic bath of deionized water.

According to embodiments, the step of anodizing said metal layer inorder to form a porous metal oxide layer is such that a layer with pores(holes) is achieved, also referred to as porous membrane. Said porousmembrane has a front main surface and a back main surface and the pores(holes) in said membrane (holes can be a set of sub-surfaceinterconnected pores) extend from the front main surface towards theback main surface.

According to embodiments the pores (holes) in said porous layer may havea length greater than ten times their width, and a width in the range5-200 nm, e.g. 20 nm or between 20 nm and 200 nm, or between 5 and 20nm.

According to the preferred embodiments, when the anodization of theadditional structure (vertical anodization) is complete, a protectivestructure is formed acting as a dielectric isolation ring surroundingthe NEMS/MEMS devices which blocks further supply of the electriccharges needed for anodization and thereby avoids unwanted extension ofthe anodized structures surrounded by the additional structure.

According to embodiments, a thin oxide barrier layer may be presentafter anodization at the bottom of the pores (holes) of the porous oxidelayer 43 and may be removed by leaving the wafer for longer time in theanodization electrolyte after the completion of the vertical anodizationprocess (after the end of the anodization current) and by further addinga small amount of an etching chemical to the anodization electrolyte.This allows for chemical etching of a very small portion of the porouslayer because the anodization electrolyte (mixture) and temperature canbe chosen to provide slow etching of the porous oxide layer (for exampleby adding a small amount of phosphoric acid which is an etchant ofaluminum oxide). The advantage of performing the barrier oxide layerremoval in the anodization electrolyte is that the inner surface of thepores (holes) is already wet upon completion of the anodization processwhich facilitates the access of the etching chemicals to the bottom ofthe pores. The oxide barrier layer may alternatively be removed by aseparate wet or dry chemical etching step after the anodization step,although difficulties are expected when attempting to use wet etchingtechniques because porous aluminum oxide may have hydrophobic propertiesthat prevent the etching chemicals from penetrating the narrow pores toreach the barrier oxide layer.

FIG. 5 a illustrates the above described barrier layer. The figureillustrates the elongate shape of the pores 60 in the anodized region 21shown in FIG. 3 c. The barrier layer is formed by the small amount 61 ofoxide at the bottom of the pores 60. By leaving the substrate in theanodization bath for a given time after the anodization current has beenstopped, the additional etchant in the bath ensures the removal of thebarrier layer (see FIG. 5 b).

According to embodiments, the step of removing the sacrificial material40 under the porous Al layer (membrane) may be performed using anetchant until said sacrificial material is at least partially removed(etched away) through the pores 60 (holes) in said porous layer 43. Thesacrificial material may be an oxide-based compound (such as SiO₂) andthe removal of this material may be performed in a reduced-pressurechamber containing a mixture of gases including an etchant of thesacrificial material (such as hydrofluoric acid) in a vapor form inaddition to other gases such as ethanol vapor, nitrogen, or water vapor.Alternatively the sacrificial layer 40 may be a polymer-based materialsuch as photoresist, which can be removed through the pores of saidporous layer 43 by dry plasma etching in a low-pressure chamber in thepresence of oxygen ions. The removal of the sacrificial material resultsin a cavity 44 that may be used to host a NEMS/MEMS structure.

According to embodiments, the sealing layer may be deposited by anevaporation technique or a chemical (CVD) or physical vapor deposition(PVD) technique in a low-pressure chamber. Said sealing layer 45 may bea conductive layer such as Al, Cu, Ni, polycrystalline Si or SiGe.Alternatively, the sealing layer 45 may be a dielectric material such asoxide- or nitride-based silicon compounds, or a polymer. Alternatively,the sealing layer may be a combination or a stack of two or morematerials. The very high aspect ratio of the pores 60 of the porousmembrane 43 prevents the deposition of the sealing layer 45 onto theNEMS/MEMS structure 50 and thus prevents damage or alteration of theNEMS/MEMS structure. Deposition of the sealing layer results in a sealedcavity 44 that may host a NEMS/MEMS device.

According to embodiments, the cavity 44 may be sealed under controlledatmosphere and pressure by controlling the gases and pressure present ina chamber used to deposit the sealing layer which in turn closes thepores (holes) 60 leading to the formation of a sealed cavity 44 withcontrolled atmosphere and pressure.

DEFINITIONS

Where reference is made in preferred embodiments to the term ‘acontrolled atmosphere’, a controlled constitution of ambient gas ismeant. The notion of ‘horizontal’ is defined as substantially orthogonalto the direction of a gravitational field, for example the earth'sgravitational field.

For the purpose of this disclosure, the notion of ‘essentially nomaterial passing through the openings’ should be understood as ‘no oronly a limited amount of material passing in and/or through theopenings’. In the context of sealing of a cavity that comprises afragile device, it should be such that the proper working of the deviceis not affected by the limited amount of material that may pass.

For the purpose of this disclosure, the term Nano- andMicro-Electro-Mechanical Systems (NEMS/MEMS) refers to miniature systemswith both electrical and non-electrical (e.g. mechanical)functionalities. Examples of NEMS/MEMS devices are inkjet printer heads,miniature mechanical switches, and sensors for applications that includeaccelerometers (e.g. for air bags in cars) and gyroscopes (e.g. forroll-over detection in cars).

For the purpose of this disclosure, the term “zero-level packaging”refers to the encapsulation of NEMS/MEMS structures at the wafer levelbefore dicing the individual NEMS/MEMS devices. Because the NEMS/MEMSstructures themselves are often freestanding and fragile they must beencapsulated at the wafer level to avoid damage during wafer dicing andin use. Additionally a porous thin film (membrane) may be part of saidencapsulation. The membrane is preferably provided directly above theNEMS/MEMS device. After removing the sacrificial layer (surrounding theNEMS/MEMS structure) through the membrane, the membrane is sealed inorder to provide the desired zero level encapsulation and to enclose therequired atmosphere at a desired pressure in the cavity. One advantageof this approach is that it reduces the thickness and area of thepackaged device compared to the traditional approach.

EXAMPLES

By way of illustration, preferred embodiments not being limited thereto,a number of further particular examples are discussed below,illustrating features and advantages of preferred embodiments.

In a first particular example, anodization of a 1 μm-thick Al layer(deposited by sputtering on top of a silicon oxide layer on 200 mm Siwafer) has been performed using a photoresist mask not including theborder line structure resulting in a large unwanted extension of theanodization region width from 160 μm up to 800 μm as shown in FIG. 2.The anodization process is performed in a Teflon-based chamber housing asulfuric acid-based electrolyte. The anodization temperature and voltageused here are within the range of 20-30° C. and 10-20V respectively. Byperforming the same anodization process of an Al layer using aphotoresist mask defining a border line 23 (ring) surrounding aplurality of other structures 21 as shown in FIG. 6, the anodizationregion width has been well controlled by the photoresist mask resultingin only approximately 6 μm lateral extension of the edges of theanodized regions 21. This means that in the areas 25, substantially noundercut of the photoresist occurs. The latter is illustrative for thegood control of the anodization process using a simple photoresist maskcomprising a borderline (ring) which surrounds the anodized region andillustrates advantages of preferred embodiments.

In a second particular example, a thin film vacuum package has beenconstructed according to preferred embodiments and the process flow ofFIGS. 4 a-4 d by following the subsequent steps:

-   -   1. Deposition and patterning of a 3 μm-thick silicon oxide layer        40 on top of a 200 mm Si wafer 10+11.    -   2. Sputter-deposition of a 1.5 μm-thick Al layer 41 on top of        the sacrificial layer 40 as shown in FIG. 4 a.    -   3. Masked anodization of the Al layer using a photoresist mask        42 in a sulfuric-acid-based electrolyte at 30° C. by applying a        constant voltage of 20V as shown in FIG. 4 b.    -   4. Upon completion of the vertical anodization process and        termination of the anodization current, the resulting porous        AlOx structures 43 are left in the anodization electrolyte for a        period of 20-30 minutes to allow for wet chemical etching of a        small portion of the AlOx layer to (at least partially) remove        the barrier AlOx layer 61 present at the bottom of the pores        (holes)—see FIG. 5.    -   5. The wafer is placed in a low-pressure chamber and exposed to        a mixture of HF vapor, ethanol vapor, and nitrogen to remove the        sacrificial layer 40 below the porous AlOx structures 43        resulting in cavities 44 as shown in FIG. 4 c.    -   6. The cavities 44 are sealed by deposition of a 4 μm-thick        silicon nitride layer 45 in a vacuum chamber using a PECVD        technique as shown in FIG. 4 c, resulting in thin film vacuum        packages as shown in FIG. 4 d.

While the invention has been illustrated and described in detail in thedrawings and foregoing description, such illustration and descriptionare to be considered illustrative or exemplary and not restrictive. Theinvention is not limited to the disclosed embodiments. Other variationsto the disclosed embodiments can be understood and effected by thoseskilled in the art in practicing the claimed invention, from a study ofthe drawings, the disclosure and the appended claims. In the claims, theword “comprising” does not exclude other elements or steps, and theindefinite article “a” or “an” does not exclude a plurality. A singleprocessor or other unit may fulfill the functions of several itemsrecited in the claims. The mere fact that certain measures are recitedin mutually different dependent claims does not indicate that acombination of these measures cannot be used to advantage. Any referencesigns in the claims should not be construed as limiting the scope.

All references cited herein are incorporated herein by reference intheir entirety. To the extent publications and patents or patentapplications incorporated by reference contradict the disclosurecontained in the specification, the specification is intended tosupersede and/or take precedence over any such contradictory material.

All numbers expressing quantities of ingredients, reaction conditions,and so forth used in the specification are to be understood as beingmodified in all instances by the term ‘about.’ Accordingly, unlessindicated to the contrary, the numerical parameters set forth herein areapproximations that may vary depending upon the desired propertiessought to be obtained. At the very least, and not as an attempt to limitthe application of the doctrine of equivalents to the scope of anyclaims in any application claiming priority to the present application,each numerical parameter should be construed in light of the number ofsignificant digits and ordinary rounding approaches.

The foregoing description details certain embodiments of the invention.It will be appreciated, however, that no matter how detailed theforegoing appears in text, the invention may be practiced in many ways,and is therefore not limited to the embodiments disclosed. It should benoted that the use of particular terminology when describing certainfeatures or aspects of the invention should not be taken to imply thatthe terminology is being re-defined herein to be restricted to includeany specific characteristics of the features or aspects of the inventionwith which that terminology is associated.

1. A method for masked anodization, comprising: Providing a substrate;providing an anodizable layer on the substrate; providing, on theanodizable layer, at least one first mask defining one or more firststructures to be anodized and an additional second mask defining asecond structure to be anodized, the second structure surrounding theone or more first structures; anodizing the anodizable layer in regionsdefined by the first and second mask in order to create the one or morefirst anodized structures and the second anodized structure; andremoving the at least one first mask and the additional second mask. 2.The method according to claim 1, wherein anodizing the anodizable layeris performed by inserting the substrate in an electrolyte and applying avoltage or electrical current to the substrate.
 3. The method accordingto claim 1, wherein anodizing the anodizable layer is performed using afirst anodizing step to form a first anodized layer, followed by asecond anodizing step after etching away the first anodized layer. 4.The method according to claim 1, wherein anodizing is performed byinserting the substrate in an electrolyte comprising at least onechemical selected from the group consisting of sulfuric acid, phosphoricacid, oxalic acid, hydrofluoric acid, ethanol, and isopropyl alcohol. 5.The method according to claim 1, wherein the anodizable layer is an Allayer and wherein anodizing is performed by inserting the substrate in asulfuric acid-based electrolyte at a temperature of from 20° C. to 40°C. and applying a voltage of about 20V.
 6. The method according to claim1, wherein anodizing produces elongated pores in the anodizedstructures, the pores extending from a front surface to a back surfaceof the anodizable layer.
 7. The method according to claim 6, wherein theanodizable layer is a metal layer which forms a metal oxide layer uponanodization, wherein anodizing is conducted in an anodization bathcomprising an etchant configured for etching the metal oxide layer, andwherein anodizing is conducted for a first time period during which thevoltage is applied, the voltage being removed at an end of the firsttime period, and for a second time period following the first timeperiod, during which the substrate is left in the anodization bath,whereby a barrier layer at the bottom of the elongated pores.
 8. Themethod according to claim 7, wherein the metal is aluminum and theetchant is phosphoric acid.
 9. The method according to claim 1, whereinproviding a substrate comprises depositing a sacrificial layer onto abase substrate, wherein the anodizable layer is provided on thesacrificial layer, wherein anodizing produces elongated pores in the oneor more first structures, the pores extending from a front surface to aback surface of the anodizable layer, wherein at least a portion of thesacrificial layer is removed through the pores so as to form a cavity,and wherein a sealing layer is applied onto the anodized structure toseal off the cavity.
 10. The method according to claim 9, wherein thesacrificial layer comprises a material selected from the groupconsisting of polycrystalline SiGe, an oxide-based film, a nitride-basedfilm, a polymer, single crystal Si, and polycrystalline Si.
 11. Themethod according to claim 9, wherein the substrate is a NEMS/MEMS deviceencapsulated in the cavity.
 12. The method according to claim 11,wherein removing at least some of the sacrificial material is performedusing a selective wet or dry etching that does not damage theencapsulated NEMS/MEMS device.
 13. The method according to claim 9,wherein the sacrificial layer is silicon oxide, and wherein removal ofthe portion of the sacrificial layer is performed in a reduced-pressurechamber using a vapor-phase hydrofluoric acid mixed with at least oneother component selected from the group consisting of nitrogen, ethanol,and water vapor.
 14. The method according to claim 9, wherein thesacrificial layer is a polymer-based material and wherein removal of theportion of the sacrificial layer is performed by dry plasma etching in alow-pressure chamber in the presence of oxygen ions.
 15. The methodaccording to claim 9, wherein the sealing layer is selected from thegroup consisting of a conductive layer, an Al layer, a Cu layer, a Nilayer, a polycrystalline Si layer, a polycrystalline SiGe layer, adielectric material, an oxide-based silicon compound, a nitride-basedsilicon compound, a polymer, combinations thereof, and stacks thereof,wherein the sealing layer is deposited is deposited in a low-pressurechamber using an evaporation technique, chemical vapor deposition, orphysical vapor deposition.
 16. The method according to claim 1, whereinthe anodizable layer is a metal layer or a semiconducting layer.
 17. Themethod according to claim 16, wherein the anodizable layer is selectedfrom the group consisting of Al, Ta, Ti, Cu, Ni, polycrystalline Si, andpolycrystalline SiGe.
 18. The method according to claim 1, wherein atleast one of the first mask and the second mask are formed byphotolithographic patterning of a photosensitive layer.